A massive data traffic increase has been witnessed recently in data centers which, in turn, has forced interconnect link-speeds from lower speeds (e.g. 10˜28 Gbps, etc.) to significantly higher speeds (e.g. 56 Gbps and up, etc.). Based on such demand, a throughput of interconnects [e.g. serializer/deserializer (SerDes), etc.] has been increased by at least a factor of two, and possibly higher.
This, in turn, has resulted in a variety of technical issues. For example, a high speed physical layer device (PHY-IC) is required, and system-level bit error rate (BER) degradation must be addressed. Specifically, since a majority of link channels built using copper printed circuit board (PCB) traces include at least two connectors (especially for backplane applications), the higher speed channel suffers from more loss and crosstalk and, therefore, bit-error performance is degraded.
To address these issues, various solutions have been proposed. One approach involves utilizing PAM4 signaling that enables two bits of information per one symbol, as opposed to one bit per symbol of non-return-to-zero (NRZ) in PAM2 that has been used in the past. Another approach involves using a full-duplex (FD) transmission system that enables bi-directional communications on the same link in both directions simultaneously, or effectively simultaneously.
However, while the use of these and other technologies enable higher link-speed, they typically require more complex, accurate, and sophisticated signal processing.